1. Field of the Invention
A hybrid data parallel/serial data transfer system, in general, and a data transfer system with phase adjustment and symbol coding for switching digital data packets in order to facilitate massive high speed transfer of information with a limited number of signal lines, in particular.
2. Prior Art
Traditionally, data transfer can take one of two forms, viz. serial or parallel. For high speed transfers, the serial stream will, typically, need to be a synchronous data stream, although asynchronous serial transfer is possible.
Conventional serial transfer, either synchronous or asynchronous, converts a byte or symbol into a single bit stream, usually with a serial clock signal included within the byte or symbol. With an embedded clock included within the data transmission, the symbol or byte can be accurately recovered. However, this process effectively results in a parallel-to-serial-to-parallel data transfer over a single signal line or path.
Conventional parallel transfer involves sending data into a parallel bus which is, typically, connected to a buffer register. After some defined delay, which allows the data line to be settled, a "Strobe" signal is then supplied to the buffer register in order to latch data into the receiving circuit or register.
Conventional high speed parallel transfer of data involves phase adjustment circuits. Each individual bit of a data transfer is fed into various delay lines to insure that the several bits arrive at the receiving data latch at the same time and that the "Strobe" arrives somewhat later with sufficient margin for the data to be reliably latched. This design limits the speed of the transfer by requiring the cycle time to be larger than the phase adjustment time of the various signal paths. Furthermore, this design requires the data signal to be valid for longer then the largest delay, which further limits the speed of the transfer.
An even higher-speed conventional parallel transfer uses synchronous transfer on each of the plurality of lines. Each line is a standard synchronous serial transfer line complete with a unique sync symbol ("SYN"). A transmitting circuit sends a byte or data to each individual line to be sent out after the initial "SYN" symbol. Thus, for N lines, N symbols are required. In addition, each line may have an uneven length depending upon whether or not the total bytes of the transmission are divisible by N. If not, some padding bytes will be needed to fill the void which represents a further waste of bandwidth.